1. Field of the Invention
The present invention relates to a semiconductor memory device having a hierarchical bit line structure.
2. Discussion of the Background
Along with an increase in capacity of a semiconductor memory device in recent years, a large-capacity memory array is connected to a pair of bit lines. As a result, a load capacity of a bit line is increased and such an increase causes reduction in operating speed.
Moreover, when reading data stored in a memory cell selected by use of bit lines with increased load capacities, a sense amplifier having a sufficiently small input offset is required for sensing small variations in amplitude of an output signal from a selected pair of bit lines. Accordingly, it is necessary to increase an area for the sense amplifier.
However, along with developments in miniaturization of semiconductors, an influence of uneven characteristics among elements is growing larger. Therefore, it becomes increasingly difficult to form a sense amplifier having a sufficiently small input offset.
Accordingly, a conceivable method for preventing reduction in operating speed and increasing detectable amplitude as much as possible is to divide a memory array to be connected in a column direction to each pair of bit lines into a plurality of sub-memory arrays. In this way, it is possible to reduce a load capacity to be applied to a bit line by means of reducing the number of memory cells to be connected thereto. As disclosed in Cangsang Zhao, Uddalak Bhattacharya, Martin Denham, Jim Kolousek, Yi Lu, Yong-Gee Ng, Novat Nintunze, Kamal Sarkez, Hemmige Varadarajan, “An 18 Mb, 12.3 GB/s CMOS Pineline-Burst Cache SRAM with 1.54 Gb/s/pin”, 1999 IEEE International Solid-State Circuits Conference, p200–201, a semiconductor memory device according to this method comprises hierarchical bit lines including local bit lines which are bit lines connected to respective sub-memory arrays, and global bit lines which are common bit lines corresponding to a plurality of sub-memory arrays on every column.
In the semiconductor memory device having the above-described hierarchical bit line structure, it is possible to transmit data inputted to the global bit line to the local bit line so as to write the data into a predetermined memory cell. A local write amplifier circuit is inserted between the global bit line and the local bit line for controlling passage of a signal from the global bit line to the local bit line. The local write amplifier circuit is controlled by a write enable signal.
In the meantime, it is necessary to charge the local bit line before reading the data stored in the memory cell. For this reason, the local bit line is provided with a precharge circuit. This precharge circuit is controlled by a precharge control signal which is generated by decoding address data.
Signal lines for controlling the local write amplifier circuits and signal lines for controlling the precharge circuits are different. Accordingly, these signal lines occupy a large circuit area.
Moreover, transfer gates and clocked transistors are used for the local write amplifier circuits to suppress signal transmission losses. Accordingly, the local write amplifier circuits occupy a relatively large circuit area. Since the local write amplifier circuit is provided in every sub-memory array, the local write amplifier circuits cause an increase in the total area of the circuit.